Qucs-GUI: /home/travis/build/Qucs/qucs/qucs/qucs/components/comp

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00001 /***************************************************************************
00002                               comp_4bit
00003                              -----------
00004     begin                : December 2008
00005     copyright            : (C) 2008 by Mike Brinson
00006     email                : mbrin72043@yahoo.co.uk
00007  ***************************************************************************/
00008 
00009 /*
00010  * comp_4bit.cpp - device implementations for comp_4bit module
00011  *
00012  * This is free software; you can redistribute it and/or modify
00013  * it under the terms of the GNU General Public License as published by
00014  * the Free Software Foundation; either version 2, or (at your option)
00015  * any later version.
00016  * 
00017  */
00018 #include "comp_4bit.h"
00019 #include "node.h"
00020 #include "misc.h"
00021 
00022 comp_4bit::comp_4bit()
00023 {
00024   Type = isComponent; // Analogue and digital component.
00025   Description = QObject::tr ("4bit comparator verilog device");
00026 
00027   Props.append (new Property ("TR", "6", false,
00028     QObject::tr ("transfer function high scaling factor")));
00029   Props.append (new Property ("Delay", "1 ns", false,
00030     QObject::tr ("output delay")
00031     +" ("+QObject::tr ("s")+")"));
00032 
00033   createSymbol ();
00034   tx = x1 + 19;
00035   ty = y2 + 4;
00036   Model = "comp_4bit";
00037   Name  = "Y";
00038 }
00039 
00040 Component * comp_4bit::newOne()
00041 {
00042   comp_4bit * p = new comp_4bit();
00043   p->Props.getFirst()->Value = Props.getFirst()->Value; 
00044   p->recreate(0); 
00045   return p;
00046 }
00047 
00048 Element * comp_4bit::info(QString& Name, char * &BitmapFile, bool getNewOne)
00049 {
00050   Name = QObject::tr("4Bit Comparator");
00051   BitmapFile = (char *) "comp_4bit";
00052 
00053   if(getNewOne) return new comp_4bit();
00054   return 0;
00055 }
00056 
00057 void comp_4bit::createSymbol()
00058 {
00059   Lines.append(new Line(-40, -90, 40,-90,QPen(Qt::darkBlue,2)));
00060   Lines.append(new Line( 40, -90, 40,100,QPen(Qt::darkBlue,2)));
00061   Lines.append(new Line( 40, 100,-40,100,QPen(Qt::darkBlue,2)));
00062   Lines.append(new Line(-40, 100,-40,-90,QPen(Qt::darkBlue,2)));
00063 
00064   Lines.append(new Line(-60,-50,-40,-50,QPen(Qt::darkBlue,2)));  // X0
00065   Lines.append(new Line(-60,-30,-40,-30,QPen(Qt::darkBlue,2)));  // X1
00066   Lines.append(new Line(-60,-10,-40,-10,QPen(Qt::darkBlue,2)));  // X2
00067   Lines.append(new Line(-60, 10,-40, 10,QPen(Qt::darkBlue,2)));  // X3
00068   Lines.append(new Line(-60, 30,-40, 30,QPen(Qt::darkBlue,2)));  // Y0
00069   Lines.append(new Line(-60, 50,-40, 50,QPen(Qt::darkBlue,2)));  // Y1
00070   Lines.append(new Line(-60, 70,-40, 70,QPen(Qt::darkBlue,2)));  // Y2
00071   Lines.append(new Line(-60, 90,-40, 90,QPen(Qt::darkBlue,2)));  // Y3
00072   Lines.append(new Line( 40, 30, 60, 30,QPen(Qt::darkBlue,2)));  // L
00073   Lines.append(new Line( 40, 10, 60, 10,QPen(Qt::darkBlue,2)));  // G
00074   Lines.append(new Line( 40,-10, 60,-10,QPen(Qt::darkBlue,2)));  // E
00075 
00076   Texts.append(new Text(-25,-85, "COMP", Qt::darkBlue, 12.0));
00077 
00078   Texts.append(new Text(-25,-40,   "{",  Qt::darkBlue, 16.0));
00079   Texts.append(new Text(-15,-35,   "X",  Qt::darkBlue, 12.0));
00080   Texts.append(new Text(-35,-63,   "0",  Qt::darkBlue, 12.0));
00081   Texts.append(new Text(-35,-43,   "1",  Qt::darkBlue, 12.0));
00082   Texts.append(new Text(-35,-23,   "2",  Qt::darkBlue, 12.0));
00083   Texts.append(new Text(-35, -3,   "3",  Qt::darkBlue, 12.0));
00084   Texts.append(new Text(-25, 42,   "{",  Qt::darkBlue, 16.0));
00085   Texts.append(new Text(-15, 47,   "Y",  Qt::darkBlue, 12.0));
00086   Texts.append(new Text(-35, 17,   "0",  Qt::darkBlue, 12.0));
00087   Texts.append(new Text(-35, 37,   "1",  Qt::darkBlue, 12.0));
00088   Texts.append(new Text(-35, 57,   "2",  Qt::darkBlue, 12.0));
00089   Texts.append(new Text(-35, 77,   "3",  Qt::darkBlue, 12.0));
00090   Texts.append(new Text(  5, 17, "X<Y",  Qt::darkBlue, 12.0));
00091   Texts.append(new Text(  5, -3, "X>Y",  Qt::darkBlue, 12.0));
00092   Texts.append(new Text(  5,-23, "X=Y",  Qt::darkBlue, 12.0));
00093 
00094   Ports.append(new Port(-60,-50));  // X0
00095   Ports.append(new Port(-60,-30));  // X1
00096   Ports.append(new Port(-60,-10));  // X2
00097   Ports.append(new Port(-60, 10));  // X3
00098   Ports.append(new Port(-60, 30));  // Y0
00099   Ports.append(new Port(-60, 50));  // Y1
00100   Ports.append(new Port(-60, 70));  // Y2
00101   Ports.append(new Port(-60, 90));  // Y3
00102   Ports.append(new Port( 60, 30));  // L
00103   Ports.append(new Port( 60, 10));  // G
00104   Ports.append(new Port( 60,-10));  // E
00105 
00106   x1 = -60; y1 = -94;
00107   x2 =  60; y2 =  104;
00108 }
00109 
00110 QString comp_4bit::vhdlCode( int )
00111 {
00112   QString s="";
00113 
00114   QString td = Props.at(1)->Value;     // delay time
00115   if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
00116   td += ";\n";
00117 
00118   QString X0    = Ports.at(0)->Connection->Name;
00119   QString X1    = Ports.at(1)->Connection->Name;
00120   QString X2    = Ports.at(2)->Connection->Name;
00121   QString X3    = Ports.at(3)->Connection->Name;
00122   QString Y0    = Ports.at(4)->Connection->Name;
00123   QString Y1    = Ports.at(5)->Connection->Name;
00124   QString Y2    = Ports.at(6)->Connection->Name;
00125   QString Y3    = Ports.at(7)->Connection->Name;
00126   QString L     = Ports.at(8)->Connection->Name;
00127   QString G     = Ports.at(9)->Connection->Name;
00128   QString E     = Ports.at(10)->Connection->Name;
00129  
00130   s = "\n  "+Name+":process ("+X0+", "+X1+", "+X2+", "+X3+", "+Y0+", "+Y1+", "+Y2+", "+Y3+")\n"+
00131       "  variable P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11 : std_logic;\n"+
00132       "  begin\n"+
00133       "    P0  := not ("+X0+" xor "+Y0+");\n"+
00134       "    P1  := not ("+X1+" xor "+Y1+");\n"+
00135       "    P2  := not ("+X2+" xor "+Y2+");\n"+
00136       "    P3  := not ("+X3+" xor "+Y3+");\n"+
00137       "    P4  := (not "+X0+") and "+Y0+";\n"+
00138       "    P5  := (not "+X1+") and "+Y1+";\n"+
00139       "    P6  := (not "+X2+") and "+Y2+";\n"+
00140       "    P7  := (not "+X3+") and "+Y3+";\n"+
00141       "    P8  := "+X0+" and (not "+Y0+");\n"+
00142       "    P9  := "+X1+" and (not "+Y1+");\n"+
00143       "    P10 := "+X2+" and (not "+Y2+");\n"+
00144       "    P11 := "+X3+" and (not "+Y3+");\n"+
00145       "    "+L+" <= P7 or (P3 and P6) or (P3 and P2 and P5) or (P3 and P2 and P1 and P4)"+td+
00146       "    "+G+" <= P11 or (P3 and P10) or (P3 and P2 and P9) or (P3 and P2 and P1 and P8)"+td+
00147       "    "+E+" <= P3 and P2 and P1 and P0"+td+  
00148       "  end process;\n";
00149   return s;
00150 }
00151 
00152 QString comp_4bit::verilogCode( int )
00153 {
00154   QString l="";
00155 
00156   QString td = Props.at(1)->Value;        // delay time
00157   if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
00158 
00159   QString X0    = Ports.at(0)->Connection->Name;
00160   QString X1    = Ports.at(1)->Connection->Name;
00161   QString X2    = Ports.at(2)->Connection->Name;
00162   QString X3    = Ports.at(3)->Connection->Name;
00163   QString Y0    = Ports.at(4)->Connection->Name;
00164   QString Y1    = Ports.at(5)->Connection->Name;
00165   QString Y2    = Ports.at(6)->Connection->Name;
00166   QString Y3    = Ports.at(7)->Connection->Name;
00167   QString L     = Ports.at(8)->Connection->Name;
00168   QString G     = Ports.at(9)->Connection->Name;
00169   QString E     = Ports.at(10)->Connection->Name; 
00170 
00171   QString LR  = "L_reg"  + Name + L;
00172   QString GR  = "G_reg"  + Name + G;
00173   QString ER  = "E_reg"  + Name + E;
00174 
00175   l = "\n  // "+Name+" 4bit comparator\n"+
00176       "  assign  "+L+" = "+LR+";\n"+
00177       "  reg     "+LR+" = 0;\n"+
00178       "  assign  "+G+" = "+GR+";\n"+
00179       "  reg     "+GR+" = 0;\n"+
00180       "  assign  "+E+" = "+ER+";\n"+
00181       "  reg     "+ER+" = 0;\n"+
00182       "  reg     P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11;\n"+
00183       "  always @ ("+X0+" or "+X1+" or "+X2+" or "+X3+" or "+Y0+" or "+Y1+" or "+Y2+" or "+Y3+")\n"+
00184       "  begin\n"+
00185       "    P0  = ~("+X0+" ^ "+Y0+");\n"+
00186       "    P1  = ~("+X1+" ^ "+Y1+");\n"+
00187       "    P2  = ~("+X2+" ^ "+Y2+");\n"+
00188       "    P3  = ~("+X3+" ^ "+Y3+");\n"+
00189       "    P4  = (~"+X0+") && "+Y0+";\n"+
00190       "    P5  = (~"+X1+") && "+Y1+";\n"+
00191       "    P6  = (~"+X2+") && "+Y2+";\n"+
00192       "    P7  = (~"+X3+") && "+Y3+";\n"+
00193       "    P8  = "+X0+" && (~"+Y0+");\n"+
00194       "    P9  = "+X1+" && (~"+Y1+");\n"+
00195       "    P10 = "+X2+" && (~"+Y2+");\n"+
00196       "    P11 = "+X3+" && (~"+Y3+");\n"+
00197       "    "+LR+" <="+td+" P7 || (P3 && P6) || (P3 && P2 && P5) || (P3 && P2 && P1 && P4)"+";\n"+
00198       "    "+GR+" <="+td+" P11 || (P3 && P10) || (P3 && P2 && P9) || (P3 && P2 && P1 && P8)"+";\n"+
00199       "    "+ER+" <="+td+" P3 && P2 && P1 && P0"+";\n"+
00200       "  end\n";
00201 
00202   return l;
00203 }