Qucs-GUI  0.0.19
/home/travis/build/Qucs/qucs/qucs/qucs/components/ha1b.cpp
Go to the documentation of this file.
00001 /***************************************************************************
00002                                ha1b
00003                               ------
00004     begin                : December 2008
00005     copyright            : (C) 2008 by Mike Brinson
00006     email                : mbrin72043@yahoo.co.uk
00007  ***************************************************************************/
00008 
00009 /*
00010  * ha1b.cpp - device implementations for ha1b module
00011  *
00012  * This is free software; you can redistribute it and/or modify
00013  * it under the terms of the GNU General Public License as published by
00014  * the Free Software Foundation; either version 2, or (at your option)
00015  * any later version.
00016  * 
00017  */
00018 #include "ha1b.h"
00019 #include "node.h"
00020 #include "misc.h"
00021 
00022 ha1b::ha1b()
00023 {
00024   Type = isComponent; // Analogue and digital component.
00025   Description = QObject::tr ("1bit half adder verilog device");
00026 
00027   Props.append (new Property ("TR", "6", false,
00028     QObject::tr ("transfer function high scaling factor")));
00029   Props.append (new Property ("Delay", "1 ns", false,
00030     QObject::tr ("output delay")
00031     +" ("+QObject::tr ("s")+")"));
00032 
00033   createSymbol ();
00034   tx = x1 + 19;
00035   ty = y2 + 4;
00036   Model = "ha1b";
00037   Name  = "Y";
00038 }
00039 
00040 Component * ha1b::newOne()
00041 {
00042   ha1b * p = new ha1b();
00043   p->Props.getFirst()->Value = Props.getFirst()->Value; 
00044   p->recreate(0); 
00045   return p;
00046 }
00047 
00048 Element * ha1b::info(QString& Name, char * &BitmapFile, bool getNewOne)
00049 {
00050   Name = QObject::tr("1Bit HalfAdder");
00051   BitmapFile = (char *) "ha1b";
00052 
00053   if(getNewOne) return new ha1b();
00054   return 0;
00055 }
00056 
00057 void ha1b::createSymbol()
00058 {
00059   Lines.append(new Line(-30, -40, 30,-40,QPen(Qt::darkBlue,2)));
00060   Lines.append(new Line( 30, -40, 30, 30,QPen(Qt::darkBlue,2)));
00061   Lines.append(new Line( 30,  30,-30, 30,QPen(Qt::darkBlue,2)));
00062   Lines.append(new Line(-30,  30,-30,-40,QPen(Qt::darkBlue,2)));
00063 
00064   Lines.append(new Line(-50,-10,-30,-10,QPen(Qt::darkBlue,2)));  // A
00065   Lines.append(new Line(-50, 10,-30, 10,QPen(Qt::darkBlue,2)));  // B
00066   Lines.append(new Line( 30, 10, 50, 10,QPen(Qt::darkBlue,2)));  // CO
00067   Lines.append(new Line( 30,-10, 50,-10,QPen(Qt::darkBlue,2)));  // S
00068 
00069   Texts.append(new Text(0, -3, "CO", Qt::darkBlue, 12.0));
00070 
00071   Lines.append(new Line(-10,-35, 10, -35, QPen(Qt::darkBlue,2)));
00072   Lines.append(new Line(-10,-35,  5, -25, QPen(Qt::darkBlue,2)));
00073   Lines.append(new Line(  5,-25,-10, -15, QPen(Qt::darkBlue,2)));
00074   Lines.append(new Line(-10,-15, 10, -15, QPen(Qt::darkBlue,2)));
00075  
00076   Ports.append(new Port(-50,-10));  // A
00077   Ports.append(new Port(-50, 10));  // B
00078   Ports.append(new Port( 50, 10));  // CO
00079   Ports.append(new Port( 50,-10));  // S
00080 
00081   x1 = -50; y1 = -44;
00082   x2 =  50; y2 =  34;
00083 }
00084 
00085 QString ha1b::vhdlCode( int )
00086 {
00087   QString s="";
00088 
00089   QString td = Props.at(1)->Value;     // delay time
00090   if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
00091   td += ";\n";
00092 
00093   QString A  = Ports.at(0)->Connection->Name;
00094   QString B  = Ports.at(1)->Connection->Name;
00095   QString CO = Ports.at(2)->Connection->Name;
00096   QString S  = Ports.at(3)->Connection->Name;
00097 
00098   s = "\n  " + Name + ":process (" + A + ", " +  B + ")\n"  +
00099       "  begin\n" +
00100       "    " + CO + " <= " + A + " and " + B + td +
00101       "    " + S  + " <= " + A + " xor " + B + td +
00102       "  end process;\n";
00103   return s;
00104 }
00105 
00106 QString ha1b::verilogCode( int )
00107 {
00108   QString td = Props.at(1)->Value;        // delay time
00109   if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
00110   
00111   QString l = "";
00112 
00113   QString A  = Ports.at(0)->Connection->Name;
00114   QString B  = Ports.at(1)->Connection->Name;
00115   QString CO = Ports.at(2)->Connection->Name;
00116   QString S  = Ports.at(3)->Connection->Name;
00117  
00118   QString COR = "CO_reg" + Name + CO;
00119   QString SR  = "S_reg"  + Name + S;
00120   
00121   l = "\n  // " + Name + " 1bit halfadder\n" +
00122       "  assign  " + CO + " = " + COR + ";\n" +
00123       "  reg     " + COR + " = 0;\n" +
00124       "  assign  " + S + " = " + SR + ";\n" +
00125       "  reg     " + SR + " = 0;\n" +
00126       "  always @ ("+ A + " or " + B +  ")\n" +
00127       "  begin\n" +
00128       "    " + COR + " <=" + td + " (" + A + " && " + B + ");\n" +
00129       "    " + SR  + " <=" + td + " (" + A + " ^ "  + B + ");\n" +
00130       "  end\n";
00131 
00132   return l;
00133 }
00134 
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Defines