Qucs-GUI  0.0.19
/home/travis/build/Qucs/qucs/qucs/qucs/components/logic_0.cpp
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00001 /***************************************************************************
00002                                logic_0
00003                               ---------
00004     begin                : December 2008
00005     copyright            : (C) 2008 by Mike Brinson
00006     email                : mbrin72043@yahoo.co.uk
00007  ***************************************************************************/
00008 
00009 /*
00010  * logic_0.cpp - device implementations for logic_0 module
00011  *
00012  * This is free software; you can redistribute it and/or modify
00013  * it under the terms of the GNU General Public License as published by
00014  * the Free Software Foundation; either version 2, or (at your option)
00015  * any later version.
00016  * 
00017  */
00018 #include "node.h"
00019 #include "logic_0.h"
00020 
00021 logic_0::logic_0()
00022 {
00023   Type = isComponent; // Analogue and digital component.
00024   Description = QObject::tr ("logic 0 verilog device");
00025 
00026   Props.append (new Property ("LEVEL", "0", false,
00027     QObject::tr ("logic 0 voltage level")
00028     +" ("+QObject::tr ("V")+")"));
00029 
00030   createSymbol ();
00031   tx = x1 + 4;
00032   ty = y2 + 4;
00033   Model = "logic_0";
00034   Name  = "S";
00035 }
00036 
00037 Component * logic_0::newOne()
00038 {
00039   logic_0 * p = new logic_0();
00040   p->Props.getFirst()->Value = Props.getFirst()->Value; 
00041   p->recreate(0); 
00042   return p;
00043 }
00044 
00045 Element * logic_0::info(QString& Name, char * &BitmapFile, bool getNewOne)
00046 {
00047   Name = QObject::tr("Logic 0");
00048   BitmapFile = (char *) "logic_0";
00049 
00050   if(getNewOne) return new logic_0();
00051   return 0;
00052 }
00053 
00054 void logic_0::createSymbol()
00055 {
00056   Lines.append(new Line(-10,  0,  0,  0,QPen(Qt::darkGreen,2)));
00057   Lines.append(new Line(-20,-10,-10,  0,QPen(Qt::darkGreen,2)));
00058   Lines.append(new Line(-20, 10,-10,  0,QPen(Qt::darkGreen,2)));
00059   Lines.append(new Line(-35,-10,-20,-10,QPen(Qt::darkGreen,2)));
00060   Lines.append(new Line(-35, 10,-20, 10,QPen(Qt::darkGreen,2)));
00061   Lines.append(new Line(-35,-10,-35, 10,QPen(Qt::darkGreen,2)));
00062 
00063   Texts.append(new Text(-30,-12, "0", Qt::darkGreen, 12.0));
00064 
00065   Ports.append(new Port(  0,  0)); // L0
00066 
00067   x1 = -39; y1 = -14;
00068   x2 = 0;   y2 =  14;
00069 }
00070 
00071 QString logic_0::vhdlCode( int )
00072 {
00073   QString s="";
00074 
00075   QString LO = Ports.at(0)->Connection->Name;
00076  
00077   s = "\n  " + Name + ":process\n" +
00078      "  begin\n    " +
00079      LO + " <= '0';\n" + 
00080      "  end process;\n";
00081   return s;
00082 }
00083 
00084 QString logic_0::verilogCode( int )
00085 {
00086   QString l = "";
00087 
00088   QString LO = Ports.at(0)->Connection->Name;
00089   
00090   QString v = "net_reg" + Name + LO;
00091   
00092   l = "\n  // " + Name + " logic 0\n" +
00093       "  assign  " + LO + " = " + v + ";\n" +
00094       "  reg     " + v + " = 0;\n" +
00095       "  initial\n" +
00096       "    " + v + " <= 0;\n";
00097 
00098   return l;
00099 }
00100 
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