Qucs-GUI  0.0.19
/home/travis/build/Qucs/qucs/qucs/qucs/components/logic_1.cpp
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00001 /***************************************************************************
00002                              logic_1
00003                             ---------
00004     begin                : December 2008
00005     copyright            : (C) 2008 by Mike Brinson
00006     email                : mbrin72043@yahoo.co.uk
00007  ***************************************************************************/
00008 
00009 /*
00010  * logic_1.cpp - device implementations for logic_1 module
00011  *
00012  * This is free software; you can redistribute it and/or modify
00013  * it under the terms of the GNU General Public License as published by
00014  * the Free Software Foundation; either version 2, or (at your option)
00015  * any later version.
00016  * 
00017  */
00018 #include "node.h"
00019 #include "logic_1.h"
00020 
00021 logic_1::logic_1()
00022 {
00023   Type = isComponent; // Analogue and digital component.
00024   Description = QObject::tr ("logic 1 verilog device");
00025 
00026  Props.append (new Property ("LEVEL", "1", false,
00027     QObject::tr ("logic 1 voltage level")
00028     +" ("+QObject::tr ("V")+")"));
00029   createSymbol ();
00030   tx = x1 + 4;
00031   ty = y2 + 4;
00032   Model = "logic_1";
00033   Name  = "S";
00034 }
00035 
00036 Component * logic_1::newOne()
00037 {
00038   logic_1 * p = new logic_1();
00039   p->Props.getFirst()->Value = Props.getFirst()->Value; 
00040   p->recreate(0); 
00041   return p;
00042 
00043 }
00044 
00045 Element * logic_1::info(QString& Name, char * &BitmapFile, bool getNewOne)
00046 {
00047   Name = QObject::tr("Logic 1");
00048   BitmapFile = (char *) "logic_1";
00049 
00050   if(getNewOne) return new logic_1();
00051   return 0;
00052 }
00053 
00054 void logic_1::createSymbol()
00055 {
00056 
00057   Lines.append(new Line(-10,  0,  0,  0,QPen(Qt::darkGreen,2)));
00058   Lines.append(new Line(-20,-10,-10,  0,QPen(Qt::darkGreen,2)));
00059   Lines.append(new Line(-20, 10,-10,  0,QPen(Qt::darkGreen,2)));
00060   Lines.append(new Line(-35,-10,-20,-10,QPen(Qt::darkGreen,2)));
00061   Lines.append(new Line(-35, 10,-20, 10,QPen(Qt::darkGreen,2)));
00062   Lines.append(new Line(-35,-10,-35, 10,QPen(Qt::darkGreen,2)));
00063 
00064   Texts.append(new Text(-30,-12, "1", Qt::darkGreen, 12.0));
00065 
00066   Ports.append(new Port(  0,  0)); // L1
00067 
00068   x1 = -39; y1 = -14;
00069   x2 = 0;   y2 =  14;
00070 }
00071 
00072 QString logic_1::vhdlCode( int )
00073 {
00074   QString s = "";
00075 
00076   QString L1 = Ports.at(0)->Connection->Name;
00077  
00078   s = "\n  " + Name + ":process\n" +
00079      "  begin\n    " +
00080      L1 + " <= '1';\n" + 
00081      "  end process;\n";
00082   return s;
00083 }
00084 
00085 QString logic_1::verilogCode( int )
00086 {
00087    
00088   QString l = "";
00089 
00090   QString L1 = Ports.at(0)->Connection->Name;
00091   
00092   QString v = "net_reg" + Name + L1;
00093   
00094   l = "\n  // " + Name + " logic 1\n" +
00095       "  assign  " + L1 + " = " + v + ";\n" +
00096       "  reg     " + v + " = 1;\n" +
00097       "  initial\n" +
00098       "    " + v + " <= 1;\n";
00099 
00100   return l;
00101 }
00102 
00103 
00104 
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