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Qucs-GUI
0.0.19
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Qucs-GUI
0.0.19
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00001 /* 00002 * pad4bit.cpp - device implementations for pad4bit module 00003 * 00004 * This is free software; you can redistribute it and/or modify 00005 * it under the terms of the GNU General Public License as published by 00006 * the Free Software Foundation; either version 2, or (at your option) 00007 * any later version. 00008 * 00009 */ 00010 #include <stdlib.h> 00011 #include "pad4bit.h" 00012 #include "node.h" 00013 00014 pad4bit::pad4bit() 00015 { 00016 Type = isComponent; // Analogue and digital component. 00017 Description = QObject::tr ("4bit pattern generator verilog device"); 00018 00019 Props.append (new Property ("Number", "0", false, 00020 QObject::tr ("pad output value"))); 00021 00022 createSymbol (); 00023 tx = x1 + 4; 00024 ty = y2 + 4; 00025 Model = "pad4bit"; 00026 Name = "Y"; 00027 } 00028 00029 Component * pad4bit::newOne() 00030 { 00031 pad4bit * p = new pad4bit(); 00032 p->Props.getFirst()->Value = Props.getFirst()->Value; 00033 p->recreate(0); 00034 return p; 00035 } 00036 00037 Element * pad4bit::info(QString& Name, char * &BitmapFile, bool getNewOne) 00038 { 00039 Name = QObject::tr("4Bit Pattern"); 00040 BitmapFile = (char *) "pad4bit"; 00041 00042 if(getNewOne) return new pad4bit(); 00043 return 0; 00044 } 00045 00046 void pad4bit::createSymbol() 00047 { 00048 Lines.append(new Line(-60, -50, 30,-50,QPen(Qt::darkGreen,2))); 00049 Lines.append(new Line( 30, -50, 30, 50,QPen(Qt::darkGreen,2))); 00050 Lines.append(new Line( 30, 50,-60, 50,QPen(Qt::darkGreen,2))); 00051 Lines.append(new Line(-60, 50,-60,-50,QPen(Qt::darkGreen,2))); 00052 00053 Lines.append(new Line( 40,-30, 30,-30,QPen(Qt::darkGreen,2))); // A 00054 Lines.append(new Line( 40,-10, 30,-10,QPen(Qt::darkGreen,2))); // B 00055 Lines.append(new Line( 40, 10, 30, 10,QPen(Qt::darkGreen,2))); // C 00056 Lines.append(new Line( 40, 30, 30, 30,QPen(Qt::darkGreen,2))); // D 00057 00058 Texts.append(new Text(-58,-46, " 0 1 2 3", Qt::darkGreen, 12.0)); 00059 Texts.append(new Text(-58,-23, " 4 5 6 7", Qt::darkGreen, 12.0)); 00060 Texts.append(new Text(-58, 0, " 8 9 10 11", Qt::darkGreen, 12.0)); 00061 Texts.append(new Text(-58, 23, "12 13 14 15", Qt::darkGreen, 12.0)); 00062 00063 Ports.append(new Port(40, 30)); // D 00064 Ports.append(new Port(40, 10)); // C 00065 Ports.append(new Port(40,-10)); // B 00066 Ports.append(new Port(40,-30)); // A 00067 00068 x1 = -64; y1 = -54; 00069 x2 = 40; y2 = 54; 00070 } 00071 00072 QString pad4bit::vhdlCode( int ) 00073 { 00074 QString v = Props.at(0)->Value; 00075 QString s1, s2, s3, s =""; 00076 00077 QString A = Ports.at(0)->Connection->Name; 00078 QString B = Ports.at(1)->Connection->Name; 00079 QString C = Ports.at(2)->Connection->Name; 00080 QString D = Ports.at(3)->Connection->Name; 00081 00082 s1 = "\n "+Name+":process\n"+ 00083 " variable n_" + Name + " : integer := " + v + ";\n" + 00084 " begin\n"; 00085 s2 = " case n_" + Name + " is\n" + 00086 " when 0 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '0';\n"+ 00087 " when 1 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '1';\n"+ 00088 " when 2 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '0';\n"+ 00089 " when 3 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '1';\n"+ 00090 " when 4 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '0';\n"+ 00091 " when 5 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '1';\n"+ 00092 " when 6 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '0';\n"+ 00093 " when 7 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '1';\n"+ 00094 " when 8 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '0';\n"+ 00095 " when 9 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '1';\n"+ 00096 " when 10 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '0';\n"+ 00097 " when 11 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '1';\n"+ 00098 " when 12 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '0';\n"+ 00099 " when 13 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '1';\n"+ 00100 " when 14 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '0';\n"+ 00101 " when 15 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '1';\n"+ 00102 " when others => null;\n" 00103 " end case;\n"; 00104 s3 = " end process;\n"; 00105 s = s1+s2+s3; 00106 return s; 00107 } 00108 00109 QString pad4bit::verilogCode( int ) 00110 { 00111 QString v = Props.at(0)->Value; 00112 00113 QString l = ""; 00114 QString l1, l2, l3; 00115 00116 QString A = Ports.at(0)->Connection->Name; 00117 QString B = Ports.at(1)->Connection->Name; 00118 QString C = Ports.at(2)->Connection->Name; 00119 QString D = Ports.at(3)->Connection->Name; 00120 00121 QString AR = "A_reg" + Name + A; 00122 QString BR = "B_reg" + Name + B; 00123 QString CR = "C_reg" + Name + C; 00124 QString DR = "C_reg" + Name + D; 00125 00126 l1 = "\n // "+Name+" 4bit pattern generator\n"+ 00127 " assign "+A+" = "+AR+";\n"+ 00128 " reg "+AR+" = 0;\n"+ 00129 " assign "+B+" = "+BR+";\n"+ 00130 " reg "+BR+" = 0;\n"+ 00131 " assign "+C+" = "+CR+";\n"+ 00132 " reg "+CR+" = 0;\n"+ 00133 " assign "+D+" = "+DR+";\n"+ 00134 " reg "+DR+" = 0;\n"+ 00135 " initial\n"; 00136 l2 = " begin\n" 00137 " case ("+v+")\n"+ 00138 " 0 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 0; "+DR+" = 0; end\n"+ 00139 " 1 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 0; "+DR+" = 1; end\n"+ 00140 " 2 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 1; "+DR+" = 0; end\n"+ 00141 " 3 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 1; "+DR+" = 1; end\n"+ 00142 " 4 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 0; "+DR+" = 0; end\n"+ 00143 " 5 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 0; "+DR+" = 1; end\n"+ 00144 " 6 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 1; "+DR+" = 0; end\n"+ 00145 " 7 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 1; "+DR+" = 1; end\n"+ 00146 " 8 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 0; "+DR+" = 0; end\n"+ 00147 " 9 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 0; "+DR+" = 1; end\n"+ 00148 " 10 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 1; "+DR+" = 0; end\n"+ 00149 " 11 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 1; "+DR+" = 1; end\n"+ 00150 " 12 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 0; "+DR+" = 0; end\n"+ 00151 " 13 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 0; "+DR+" = 1; end\n"+ 00152 " 14 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 1; "+DR+" = 0; end\n"+ 00153 " 15 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 1; "+DR+" = 1; end\n"+ 00154 " endcase\n"; 00155 l3 = " end\n"; 00156 l = l1+l2+l3; 00157 return l; 00158 }
1.7.6.1
