- l -

• LabelDialog() : LabelDialog
• launchTool() : QucsApp
• LibComp() : LibComp
• LibraryDialog() : LibraryDialog
• Line() : Line
• load() : Graph , Painting , PortSymbol , Marker , Rectangle , QucsDoc , Arrow , Schematic , TextDoc , Ellipse , Wire , WireLabel , Component , EllipseArc , GraphicLine , Diagram , GraphicText , ID_Text
• loadASCOout() : Optimize_Sim
• loadComponents() : Schematic
• loadDatFile() : Graph
• loadDiagrams() : Schematic
• LoadDialog() : LoadDialog
• loadDocument() : Schematic
• loadFile() : VHDL_File , Verilog_File
• loadGraphData() : Diagram
• loadIndepVarData() : Graph
• loadIntoNothing() : Schematic
• loadPaintings() : Schematic
• loadProperties() : Schematic
• loadSection() : LibComp
• loadSelected() : LoadDialog
• loadSettings() : TextDoc
• loadSimulationTime() : TextDoc
• loadSpiceNetList() : SpiceDialog
• loadSymbol() : LibComp , Subcircuit
• loadVarData() : DiagramDialog
• loadWires() : Schematic
• log_amp() : log_amp
• logic_0() : logic_0
• logic_1() : logic_1
• Logical_AND() : Logical_AND
• Logical_Buf() : Logical_Buf
• Logical_Inv() : Logical_Inv
• Logical_NAND() : Logical_NAND
• Logical_NOR() : Logical_NOR
• Logical_OR() : Logical_OR
• Logical_XNOR() : Logical_XNOR
• Logical_XOR() : Logical_XOR